Integrated circuits have become progressively more miniaturised since their invention in 1959. Initially, their performance was improved by reducing the size of transistors used in the circuits, because the size reduction produced a reduction in parasitic capacitances of the circuit and a reduction in power dissipation. The miniaturisation was achieved by linearly scaling down the size of the features of the integrated circuit, by miniaturising the scale of the lithographic masks used in the manufacturing process.
However, as the scale of the devices was reduced further, it was found that the electrical characteristics of the resulting circuit did not scale linearly, and as a result, the configuration of the individual transistors in the circuit needed to be modified in order to optimise performance.
For example, current leakage from individual transistors of the circuits becomes a prominent factor degrading device performance as the device is miniaturised further and in high capacity dynamic random access memory (DRAM) cells, complex, three dimensional capacitors have been proposed in order to compensate for leakage current. However, the fabrication of such capacitors becomes unduly complicated.
Recently an alternative approach has been demonstrated, applicable to integrated circuits, in which transport of individual groups of electrons, in theory single electrons, is controlled. Reference is directed to “Single-electron memory”, K. Nakazato, R. J. Blaikie and H. Ahmed, J. Appl. Phys. 75, 5123 (1994). A single electron memory is disclosed in WO94/15340. In this device, a small group of electrons, e.g., less than ten electrons, is stored at a node, which consists of an island constructed on the nanometer scale by electron beam lithography. The charge that can exist at the node is limited by the so-called Coulomb blockade effect. Once charged with the small group of electrons, no additional electrons can enter the island, due to its charging energy. In order to demonstrate the Coulomb blockade effect, the charging energy of the island needs to exceed the surrounding thermal energy, so that thermal electrons do not swamp the charge of the island. This requires either the device to be cooled to liquid nitrogen temperatures to reduce the thermal energy or, if the device is to operate at room temperature, the scale of the island needs to be of the order of 1 or 2 nm, which is beyond the capability of current e-beam lithographic techniques.
Charge is caused to enter and leave the island by means of a multiple tunnel junction device. In the device disclosed in WO94/15340 supra, the multiple tunnel junction device comprises a side gated structure which gives rise to multiple, stable electron states on the island, which can be used to provide a memory.
It has previously been proposed to improve the characteristics of a conventional transistor, which operates using a conventional current, which comprises many thousands of electrons per second, by associating a multiple tunnel junction device with the gate of the transistor, so that when in the off state, the multiple tunnel junction device minimises leakage current. Reference is directed to our EP-A-0 649 174. In this device, the gate is provided with a finger structure, constructed on the nanometer scale so as to produce, e.g., by a field effect, a series of tunnel barriers in the source-drain path of the transistor. The multiple barriers act as a multiple tunnel junction so that in the off state, electron transport through the device is limited by Coulomb blockade, thereby significantly reducing leakage current from the drain to the source. However, this device is difficult to manufacture because the finger members formed in the gate need to be fabricated on a nanometer scale and current technologies do not permit such a device to be constructed readily on a scale small enough for operation at room temperature. In “Superlattice tailoring to obtain devices with high saturation velocity” IBM Technical Disclosure Bulletin, Vol 29. No 7, December 1986, pp 2931–2, a transistor is described which has a superlattice in its source-drain path, formed of overlying, conductive layers of opposite conductivity type. The superlattice gives rise to energy subbands or minibands which allow the overall electron velocity to be increased.
In our EP 96308283.9 filed on 15 Nov. 1996, and corresponding U.S. Ser. No. 08/958,845 filed on 28 Oct. 1997 there is described a memory device which includes a memory node to which charge is written through a tunnel barrier configuration from a control electrode. The stored charge affects the conductivity of a source-drain path and data is read by monitoring the conductivity of the path. The charge barrier configuration comprises a multiple tunnel barrier which may comprise alternating layers of polysilicon of 5 nm thickness and layers of silicon nitride of 2 nm thickness, overlying a polycrystalline layer of silicon, part of which acts as a memory node. Alternative barrier configurations are described including conductive nanometer scale conductive islands which act as a memory node, distributed in an insulating matrix. The advantage of the tunnel barrier configuration is that it reduces leakage current from the memory node without degrading the reading and writing times for the memory. Different types of memory device are described. In a first type, charge carriers from a control electrode pass through the tunnel barrier configuration to the memory node in response to a voltage applied to the control electrode. In a second type of device, an additional gate is provided for the tunnel barrier configuration in order to control the transfer of charge carriers from the control electrode to the memory node.